In semiconductor manufacturing, a design layout of a wafer pattern is typically checked or verified to determine whether the layout meets certain design specification requirements. In particular, the design layout is checked against a plurality of design rules to determine whether the layout properly complies with these rules. Currently, utilities that check design rules utilize very simply or basic comparisons, such as comparing a feature width to a minimum width requirement or comparing a spacing between different features to a minimum spacing requirement. However, a design layout that satisfies the design rules may still be subject to certain hot spots, or potential sources of defect. Therefore, a need exists for a method that checks a design layout for additional problem areas, such as hot spots.